This sample project demonstrates some of the features of the
spice-noqsi back end for lepton-netlist. There is brief reference
documentation on these features in the README in the main
gnet-spice-noqsi directory.

To run the demo, you must have ngspice installed. Typing "make"
should create netlists, run ngspice, and display a plot of the
frequency response of a broadband amplifier.

Some details:

This project handles hierarchy in SPICE rather than
lepton-netlist. Thus, hierarchy traversal is disabled in
configuration. This spice-noqsi back end does not require this:
you may instead allow lepton-netlist to flatten hierarchy and pass
the flattened netlist to SPICE. Either approach works. The
BBamp.sch schematic should be usable as-is in a printed circuit
design flow as well, but in that case you'll probably need to let
lepton-netlist traverse the hierarchy.

The BBamp.sch schematic is the amplifier itself. Its symbol is
included in the drawing as a graphical comment for the reader,
using a graphical=1 attribute. A toplevel "spice-prolog=.subckt
BBamp %up" attribute creates the .subckt "card" using the %up
function. It is mirrored by a "spice-prototype=X? %down BBamp"
attribute in the symbol itself. The SPICE code generated by this
pair of attributes mimics the semantics of hierarchy traversal in
lepton-netlist. The symbol also contains "file=BBamp.cir". This
generates ".INCLUDE BBamp.cir" in the higher level SPICE netlist.

Most components in this schematic use the default prototypes built
into spice-noqsi. The default for a transistor needs a model-name
attribute: Q2 has "model-name=fastpnp" attached. The model for Q1
is subcircuit, not a primitive SPICE model, so the default won't
work. It needs a spice-prototype attribute. The attribute value
here, "X? #C #B #E fastnpn", demonstrates prefix modification
("Q1" becomes "XQ1") and the use of pinnumber rather than the
default pinseq for ordering the net connections.

The toplevel schematic "AC.sch" contains a toplevel spice-epilog
attribute. This generates the code for the analysis to run and the
output to generate.

The Makefile has a "wildcard" rule for generating a SPICE netlist
from a single-page schematic. For multipage schematics you'll need
to be more explicit. The "simulation" target forces the generation
of the netlist files and runs SPICE. Since I didn't use the
"file=" mechanism to include the transistor models, I explicitly
load the model library into SPICE here.




